1 Field of the Invention
The present invention relates to the field of semiconductor processing; and more specifically to the field of polishing methods and apparatuses for planarizing thin films formed over a semiconductor substrate.
2 Description of Related Art
Integrated circuits (IC's) manufactured today generally rely upon an elaborate system of metalization interconnects to couple the various devices which have been fabricated in the semiconductor substrate. The technology for forming these metalized interconnects is extremely sophisticated and well understood by practitioners in the art.
Commonly, aluminium or some other metal is deposited and then patterned to form interconnect paths along the surface of the silicon substrate. In most processes, a dielectric or insulated layer is then deposited over this first metal (metal 1) layer; via openings are etched through the dielectric layer and the second metalization layer is deposited. The second metal layer covers the dielectric layer and fills the via openings, thereby making electrical contact down to the metal 1 layer. The purpose of the dielectric layer, of course, is to act as an insulator between the metal 1 and metal 2 interconnects. Most often the intermetal dielectric layer comprises a chemical vapor deposition (CVD) of silicon dioxide which is normally formed to a thickness of approximately one micron. (Conventionally the underlying metal 1 interconnects are also formed to a thickness of approximately one micron.) This silicon dioxide layer covers the metal 1 interconnects conformably such that the upper surface of the silicon dioxide layer is characterized by a series of nonplanar steps which correspond in height and width to the underlying metal 1 lines.
These step height variations in the upper surface of the interlayer dielectric have several undesirable features. First of all, nonplaner dielectric surfaces interfere with optical resolution of subsequent photolithographic processing steps. This makes it extremely difficult to print high resolution lines. A second problem involves the step coverage of metal 2 (second metal) layer over the interlayer dielectric. If the step height is too large there is a serious danger that open circuits will be formed in metal 2 layer.
To combat these problems, various techniques have been developed in an attempt to planarize the upper surface of the interlayer dielectric (ILD). One approach employs abrasive polishing to remove the protruding steps along the upper surface of the dielectric. According to this method, the silicon substrate is placed face down on a table covered with a flat pad which has been coated with an abrasive material (slurry). Both the wafer and the table are then rotated relative to each other to remove the protruding portions. This abrasive polishing process continues until the upper surface of the dielectric layer is largely flattened.
One factor in achieving and maintaining a high and stable polishing rate is pad conditioning. Pad conditioning is a technique whereby the pad surface is put into a proper state for subsequent polishing work. In one conditioning method, as shown in FIG. 1, the polishing pad 12 is impregnated with a plurality of macrogrooves 14. Polishing pad 12 is shown in FIG. 1 having a series of substantially circumferential grooves 14 formed across the portion of the pad over which polishing takes place. The macrogrooves aid in polishing by channeling slurry between the substrate surface and the pad. The macrogrooves 14 are formed prior to polishing by means of a milling machine, a lathe, a press or similar method. Since polishing does not normally occur across the entire pad surface, the grooves are normally only formed into a portion of the pad over which polishing takes place. This is shown in FIG. 1 by the grove path area 16.
FIG. 2 illustrates a cross section of grooved path area 16 formed on the pad 12. As can be seen, the grooves are characteristically triangular shaped (but may have other shapes as well), and have an initial depth which is sufficient to allow slurry to channel beneath the substrate surface during polishing. The depth of the macrogrooves is approximately 300 microns. The spacing of the grooves varies from about two grooves per radial inch to 32 grooves per radial inch.
A problem with this technique of conditioning the pad is that over time, the one time provided macrogrooves become worn down due to polishing. This is shown by the broken line 18 in FIG. 1. As polishing occurs, pad 11 gets worn away and the added macrogrooves become smoothed over. A smooth pad surface results in a reduction of slurry delivery beneath the wafer. The degradation in pad roughness over time results in low, unstable, and unpredictable polish rates. Low polish rates decrease wafer throughput. Unstable and unpredictable polish rates make the planarization process unmanufacturable since one can only estimate the amount of ILD removed from wafer to wafer. Additionally, when the pad roughness becomes "glazed" or "smoothed" over time, rough wafers polish at a different, higher rate than do smooth wafers. That is, wafers which have rough surfaces from, for example, laser scribe lines, polish at faster rates because their surfaces "rough" the pad surface while they polish. This increases slurry delivery beneath these wafers which accounts for the rise in polish rate. Thus, the polish rate of wafers polished with the earlier method is dependant upon wafer type. Different polish rates for different types of wafers make the polishing process unmanufacturable.
Thus, what is desired is an apparatus and method for mechanically polishing a thin film wherein the polish rate is high, stable, and independent of wafer type.